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2k x 8 dual-port static ram cy7c132, cy7c136 cy7c136a, cy7c142, cy7c146 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-06031 rev. *g revised november 24, 2010 features true dual-ported memory cells that enable simultaneous reads of the same memory location 2k x 8 organization 0.65 micron cmos for optimum speed and power high speed access: 15 ns low operating power: i cc = 110 ma (maximum) fully asynchronous operation automatic power down master cy7c132/cy7c136/cy7c136a [1] easily expands data bus width to 16 or more bits using slave cy7c142/cy7c146 busy output flag on cy7c 132/cy7c136/cy7c136a; busy input on cy7c142/cy7c146 int flag for port to port communication (52-pin plcc/pqfp versions) cy7c136, cy7c136a, and cy7c146 available in 52-pin plcc and 52-pin pqfp packages pb-free packages available functional description the cy7c132, cy7c136, cy7c 136a, cy7c142, and cy7c146 are high speed cmos 2k x 8 dual-port static rams. two ports are provided to permit independent access to any location in memory. the cy7c132, cy7c136, and cy7c136a can be used as either a standalone 8-bit dual-port static ram or as a master dual-port ram, in conjunction with the cy7c142/cy7c146 slave dual-port device. they are used in systems that require 16- bit or greater word widths. this is the solution to applications that require shared or buffered data, such as cache memory for dsp, bit-sl ice, or multiprocessor designs. each port has independent control pins; chip enable (ce ), write enable (r/w ), and output enable (oe ). busy flags are provided on each port. in addition , an interrupt flag (int ) is provided on each port of the 52-pin plcc version. busy signals that the port is trying to access the same location current ly being accessed by the other port. on the plcc version, int is an interrupt flag indicating that data is placed in an unique location (7ff for the left port and 7fe for the ri ght port). an automatic power down featur e is controlled independently on each port by the chip enable (ce ) pins. r/w l busy l ce l oe l a 10l a 0l a 0r a 10r r/w r ce r oe r ce r oe r ce l oe l r/w l r/w r i/o 7l i/o 0l i/o 7r i/o 0r busy r int l int r arbitration logic (7c132/7c136 only) and interruptlogic (7c136/7c146 only) control i/o control i/o memory array address decoder address decoder [2] [3] [3] [2] logic block diagram notes 1. cy7c136 and cy7c136a are functionally identical. 2. cy7c132/cy7c136/cy7c136a (master): busy is open drain output and requires pull up resistor. cy7c142/cy7c146 (slave): busy is input. 3. open drain outputs; pull up resistor required. [+] feedback
cy7c132, cy7c136 cy7c136a, cy7c142, cy7c146 document #: 38-06031 rev. *g page 2 of 15 pinouts figure 1. 52-pin plcc (top view) figure 2. 52-pin pqfp (top view) selection guide specification 7c136-15 [4] 7c146-15 7c132-25 [4] 7c136-25 7c142-25 7c146-25 7c132-30 7c136-30 7c142-30 7c146-30 7c132-35 7c136-35 7c142-35 7c146-35 7c132-45 7c136-45 7c142-45 7c146-45 7c132-55 7c136-55 7c136a-55 7c142-55 7c146-55 unit maximum access time 15 25 30 35 45 55 ns maximum operating current com?l/ind 190 170 170 120 120 110 ma maximum standby current com?l/ind 75 65 65 45 45 35 ma shaded areas contain preliminary information. 1 v cc oe r a 0r 8 9 10 11 12 13 14 15 16 17 18 19 20 46 45 44 43 42 41 40 39 38 37 36 35 34 2122 23 24 25 26 27 28 29 30 31 32 33 7 6 5 4 3 2 52 51 50 49 48 47 a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r nc i/o 7r a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l i/o 2l i/o 3l i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o 4l 5l 6l 7l 0r 1r 2r 3r 4r 5r 6r nc gnd oe busy int a r/w ce r/w busy int 0l l l l l l ce r r r r 7c136/7c136a 7c146 a 10l a 10r 46 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 1415 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 45 44 43 42 41 40 v cc oe busy int a r/w ce r/w busy int 0l l l l l l ce r r r r oe r a 0r a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r nc i/o 7r a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l i/o 2l i/o 3l i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o 4l 5l 6l 7l 0r 1r 2r 3r 4r 5r 6r nc gnd 7c136/7c136a 7c146 a 10l a 10r note: 4. 15 ns and 25 ns version available in pqfp and plcc packages only. [+] feedback
cy7c132, cy7c136 cy7c136a, cy7c142, cy7c146 document #: 38-06031 rev. *g page 3 of 15 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ..................................... ? 65c to +150c ambient temperature with power applied .................................................. ? 55c to +125c supply voltage to ground potential (pin 48 to pin 24) .................................................? 0.5v to +7.0v dc voltage applied to outputs in high z state .....................................................? 0.5v to +7.0v dc input voltage ................................................. ? 3.5v to +7.0v output current into outputs (l ow)............................. 20 ma static discharge voltage.......................................... > 2001v (per mil-std-883, method 3015) latch up current.................................................... > 200 ma operating range range ambient temperature v cc commercial 0c to +70c 5v 10% industrial ?40c to +85c 5v 10% notes 5. busy and int pins only. 6. duration of the short circ uit should not exceed 30 seconds. 7. at f = f max , address and data inputs are cycling at the maximum frequency of read cycle of 1/t rc and using ac test waveforms input levels of gnd to 3v. electrical characteristics over the operating range parameter description test conditions 7c136-15 [4] 7c146-15 7c132-30 [4] 7c136-25, 30 7c142-30 7c146-25, 30 7c132-35,45 7c136-35,45 7c142-35,45 7c146-35,45 7c132-55 7c136-55 7c136a-55 7c142-55 7c146-55 unit min max min max min max min max v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 2.4 2.4 v v ol output low voltage i ol = 4.0 ma 0.4 0.4 0.4 0.4 v i ol = 16.0 ma [5] 0.5 0.5 0.5 0.5 v ih input high voltage 2.2 2.2 2.2 2.2 v v il input low voltage 0.8 0.8 0.8 0.8 v i ix input load current gnd < v i < v cc ?5 +5 ? 5+5 ? 5+5 ? 5+5 a i oz output leakage current gnd < v o < v cc , output disabled ?5 +5 ? 5+5 ? 5+5 ? 5+5 a i os output short circuit current [6] v cc = max., v out = gnd ?350 ? 350 ? 350 ? 350 ma i cc v cc operating supply current ce = v il , outputs open, f = f max [7] com?l/ ind?l 190 170 120 110 ma i sb1 standby current both ports, ttl inputs ce l and ce r > v ih , f = f max [7] com?l/ ind?l 75 65 45 35 ma i sb2 standby current one port, ttl inputs ce l or ce r > v ih , active port outputs open, f = f max [7] com?l/ ind?l 135 115 90 75 ma i sb3 standby current both ports, cmos inputs both ports ce l and ce r > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v, f = 0 com?l/ ind?l 15 15 15 15 ma i sb4 standby current one port, cmos inputs one port ce l or ce r > v cc ? 0.2v, v in > v cc ? 0.2v or v in < 0.2v, active port outputs open, f = f max [7] com?l/ ind?l 125 105 85 70 ma shaded areas contain preliminary information. [+] feedback
cy7c132, cy7c136 cy7c136a, cy7c142, cy7c146 document #: 38-06031 rev. *g page 4 of 15 capacitance this parameter is guaranteed but not tested. parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 15 pf c out output capacitance 10 pf figure 3. ac test loads and waveforms 3.0v 5v output r1 893 r2 347 30 pf including jig and scope gnd 90% 90% 10% <5ns <5 ns 5v output r1 893 r2 347 5pf including jig and scope (a) (b) output 1.4v equivalent to: th venin equivalent 5v 281 30 pf busy or int busy output load (cy7c132/cy7c136 only) 10% all input pulses 250 switching characteristics over the operating range (speeds -15, -25, -30) [8] parameter description 7c136-15 [4] 7c146-15 7c132-25 [4] 7c136-25 7c142-25 7c146-25 7c132-30 7c136-30 7c142-30 7c146-30 unit min max min max min max read cycle t rc read cycle time 15 25 30 ns t aa address to data valid [9] 15 25 30 ns t oha data hold from address change 0 00ns t ace ce low to data valid [9] 15 25 30 ns t doe oe low to data valid [9] 10 15 20 ns t lzoe oe low to low z [7, 10] 3 33ns t hzoe oe high to high z [7, 10, 11] 10 15 15 ns t lzce ce low to low z [7, 10] 3 55ns t hzce ce high to high z [7, 10, 11] 10 15 15 ns t pu ce low to power up [7] 0 00ns t pd ce high to power down [7] 15 25 25 ns shaded areas contain preliminary information. notes 8. test conditions assume signal transition times of 5 ns or less , timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v and output loading of the specified i ol /i oh, and 30 pf load capacitance. 9. ac test conditions use v oh = 1.6v and v ol = 1.4v. 10. at any given temperature and voltag e condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe . 11. t lzce , t lzwe , t hzoe , t lzoe, t hzce, and t hzwe are tested with c l = 5pf as in (b) of ac test loads and waveforms . transition is measured 500 mv from steady state voltage. [+] feedback
cy7c132, cy7c136 cy7c136a, cy7c142, cy7c146 document #: 38-06031 rev. *g page 5 of 15 write cycle [12] t wc write cycle time 15 25 30 ns t sce ce low to write end 12 20 25 ns t aw address setup to write end 12 20 25 ns t ha address hold from write end 2 22ns t sa address setup to write start 0 00ns t pwe r/w pulse width 12 15 25 ns t sd data setup to write end 10 15 15 ns t hd data hold from write end 0 00ns t hzwe r/w low to high z [7] 10 15 15 ns t lzwe r/w high to low z [7] 0 00ns busy/interrupt timing t bla busy low from address match 15 20 20 ns t bha busy high from address mismatch [13] 15 20 20 ns t blc busy low from ce low 15 20 20 ns t bhc busy high from ce high [13] 15 20 20 ns t ps port set up for priority 5 55ns t wb r/w low after busy low [14] 0 00ns t wh r/w high after busy high 13 20 30 ns t bdd busy high to valid data 15 25 30 ns t ddd write data valid to read data valid note 15 note 15 note 15 ns t wdd write pulse to data delay note 15 note 15 note 15 ns interrupt timing [16] t wins r/w to interrupt set time 15 25 25 ns t eins ce to interrupt set time 15 25 25 ns t ins address to interrupt set time 15 25 25 ns t oinr oe to interrupt reset time [13] 15 25 25 ns t einr ce to interrupt reset time [13] 15 25 25 ns t inr address to interrupt reset time [13] 15 25 25 ns shaded areas contain preliminary information. switching characteristics over the operating range (speeds -15, -25, -30) [8] (continued) parameter description 7c136-15 [4] 7c146-15 7c132-25 [4] 7c136-25 7c142-25 7c146-25 7c132-30 7c136-30 7c142-30 7c146-30 unit min max min max min max notes 12. the internal write time of the memory is defined by the overlap of ce low and r/w low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write. 13. these parameters are measured from the input signal changing, until the output pin goes to a high impedance state. 14. cy7c142/cy7c146 only. 15. a write operation on port a, where port a has priority, leaves the data on port b?s outputs undisturbed until one access tim e after one of the following: busy on port b goes high. port b?s address toggled. ce for port b is toggled. r/w for port b is toggled during valid read. 16. 52-pin plcc and pqfp versions only. [+] feedback
cy7c132, cy7c136 cy7c136a, cy7c142, cy7c146 document #: 38-06031 rev. *g page 6 of 15 switching characteristics over the operating range (speeds -35, -45, -55) [8] parameter description 7c132-35 7c136-35 7c142-35 7c146-35 7c132-45 7c136-45 7c142-45 7c146-45 7c132-55 7c136-55 7c136a-55 7c142-55 7c146-55 unit min max min max min max read cycle t rc read cycle time 35 45 55 ns t aa address to data valid [9] 35 45 55 ns t oha data hold from address change 0 0 0 ns t ace ce low to data valid [9] 35 45 55 ns t doe oe low to data valid [9] 20 25 25 ns t lzoe oe low to low z [7, 10] 333ns t hzoe oe high to high z [7, 10, 11] 20 20 25 ns t lzce ce low to low z [7, 10] 555ns t hzce ce high to high z [7, 10, 11] 20 20 25 ns t pu ce low to power up [7] 000ns t pd ce high to power down [7] 35 35 35 ns write cycle [12] t wc write cycle time 35 45 55 ns t sce ce low to write end 30 35 40 ns t aw address setup to write end 30 35 40 ns t ha address hold from write end 2 2 2 ns t sa address setup to write start 0 0 0 ns t pwe r/w pulse width 25 30 30 ns t sd data setup to write end 15 20 20 ns t hd data hold from write end 0 0 0 ns t hzwe r/w low to high z [7] 20 20 25 ns t lzwe r/w high to low z [7] 000ns busy/interrupt timing t bla busy low from address match 20 25 30 ns t bha busy high from address mismatch [13] 20 25 30 ns t blc busy low from ce low 20 25 30 ns t bhc busy high from ce high [13] 20 25 30 ns t ps port set up for priority 5 5 5 ns t wb r/w low after busy low [14] 000ns t wh r/w high after busy high 30 35 35 ns t bdd busy high to valid data 35 45 45 ns t ddd write data valid to read data valid note 15 note 15 note 15 ns t wdd write pulse to data delay note 15 note 15 note 15 ns [+] feedback
cy7c132, cy7c136 cy7c136a, cy7c142, cy7c146 document #: 38-06031 rev. *g page 7 of 15 interrupt timing [16] t wins r/w to interrupt set time 25 35 45 ns t eins ce to interrupt set time 25 35 45 ns t ins address to interrupt set time 25 35 45 ns t oinr oe to interrupt reset time [13] 25 35 45 ns t einr ce to interrupt reset time [13] 25 35 45 ns t inr address to interrupt reset time [13] 25 35 45 ns switching characteristics over the operating range (speeds -35, -45, -55) [8] (continued) parameter description 7c132-35 7c136-35 7c142-35 7c146-35 7c132-45 7c136-45 7c142-45 7c146-45 7c132-55 7c136-55 7c136a-55 7c142-55 7c146-55 unit min max min max min max switching waveforms figure 4. read cycle no. 1 (either port-address access) [17, 18] figure 5. read cycle no. 2 (either port-ce /oe ) [17, 19] t rc t aa t oha data valid previous data valid data out address t ace t lzoe t doe t hzoe t hzce data valid data out ce oe t lzce t pu i cc i sb t pd notes 17. r/w is high for read cycle. 18. device is continuously selected, ce = v il and oe = v il . 19. address valid prior to or coincident with ce transition low. [+] feedback
cy7c132, cy7c136 cy7c136a, cy7c142, cy7c146 document #: 38-06031 rev. *g page 8 of 15 figure 6. read cycle no. 3 (read with busy master: cy7c132 and cy7c136/cy7c136a) figure 7. write cycle no.1 (oe three-states data i/os?either port) [12, 20] switching waveforms (continued) t bha t bdd valid t ddd t wdd address match address match r/w r address r d inr address l busy l dout l t ps t bla t rc t pwe valid t aw t wc data valid high impedance t sce t sa t pwe t hd t sd t ha t hzoe ce r/w address oe d out data in note 20. if oe is low during a r/w controlled write cycle, the write pulse width must be the larger of t pwe or t hzwe + t sd to allow the data i/o pins to enter high impedance and for data to be placed on the bus for the required t sd . [+] feedback
cy7c132, cy7c136 cy7c136a, cy7c142, cy7c146 document #: 38-06031 rev. *g page 9 of 15 figure 8. write cycle no. 2 (r/w three-states data i/os?either port) [12, 21] figure 9. busy timing diagram no. 1 (ce arbitration) switching waveforms (continued) t aw t wc t sce t sa t pwe t hd t sd t hzwe t ha high impedance ce r/w address d out data in t lzwe data valid address match t ps ce l valid first: t blc t bhc address match t ps t blc t bhc busy l ce r ce l address l,r busy r ce l ce r address l,r ce r valid first: note 21. if the ce low transition occurs simultaneously with or after the r/w low transition, the outputs remain in a high impedance state. [+] feedback
cy7c132, cy7c136 cy7c136a, cy7c142, cy7c146 document #: 38-06031 rev. *g page 10 of 15 figure 10. busy timing diagra m no. 2 (address arbitration) figure 11. busy timing diagram no. 3 (write with busy , slave: cy7c142/cy7c146) switching waveforms (continued) left address valid first: address match t ps address l busy r address mismatch t rc or t wc t bla t bha address r address match address mismatch t ps address l busy l t rc or t wc t bla t bha address r right address valid first: t pwe t wb t wh busy r/w ce [+] feedback
cy7c132, cy7c136 cy7c136a, cy7c142, cy7c146 document #: 38-06031 rev. *g page 11 of 15 interrupt timing diagrams [16] figure 12. left side sets int r figure 13. right side clears int r figure 14. right side sets int l figure 15. right side clears int l switching waveforms (continued) write 7ff t ins address l r/ w l t wc t eins ce l t ha t sa t wins int r read 7ff t rc t einr t ha t inr t oinr address r ce r r/w r int r oe r write 7fe t ins address r r/w r t wc t eins ce r t ha t sa t wins int l read 7fe t einr t ha t inr t oinr address l ce l r/ w l int l oe l t rc [+] feedback
cy7c132, cy7c136 cy7c136a, cy7c142, cy7c146 document #: 38-06031 rev. *g page 12 of 15 figure 16. typical dc and ac characteristics 1.4 1.0 0.4 4.0 4.5 5.0 5.5 6.0 ?55 25 125 1.2 1.0 120 100 80 60 40 20 0 1.0 2.0 3.0 4.0 output source current (ma) supply voltage (v) normalized supply current vs. supply voltage normalized supply current vs. ambient temperature ambient temperature (c) output voltage (v) output source current vs. output voltage 0.0 0.8 0.8 0.6 0.6 normalized i cc , i sb v cc = 5.0v v in = 5.0v t a = 25c 0 i cc i cc 1.6 1.4 1.2 1.0 0.8 ?55 125 normalized t aa normalized access time vs. ambient temperature ambient temperature (c) 1.4 1.3 1.2 1.0 0.9 4.0 4.5 5.0 5.5 6.0 normalized t aa supply voltage (v) normalized access time vs. supply voltage 120 140 100 60 40 20 0.0 1.0 2.0 3.0 4.0 output sink current (ma) 0 80 output voltage (v) output sink current vs. output voltage 0.6 0.8 1.25 1.0 0.75 10 40 normalized i cc 0.50 normalized i cc vs. cycle time cycle frequency (mhz) 3.0 2.5 2.0 1.5 0.5 0 1.0 2.0 3.0 5.0 normalized t pc 25.0 30.0 20.0 10.0 5.0 0 200 400 600 800 delta t aa (ns) 0 15.0 0.0 supply voltage (v) typical power-on current vs. supply voltage capacitance (pf) typical access time change vs. output loading 4.0 1000 1.0 20 30 0.2 0.6 1.2 i sb3 0.2 0.4 i sb3 25 1.1 v in = 0.5v normalized i cc , i sb v cc = 5.0v t a = 25c v cc = 5.0v v cc = 5.0v t a = 25c t a = 25c v cc = 4.5v v cc = 5.0v t a = 25c [+] feedback
cy7c132, cy7c136 cy7c136a, cy7c142, cy7c146 document #: 38-06031 rev. *g page 13 of 15 ordering code definitions ordering information speed (ns) ordering code package diagram package type operating range 25 cy7c136-25jxc 51-85004 52-pin plastic leaded chip carrier (pb-free) commercial cy7c136-25nc 51-85042 52-pin plastic quad flatpack cy7c136-25nxc 52-pin plastic quad flatpack (pb-free) CY7C136-25JXI 51-85004 52-pin plastic leaded chip carrier (pb-free) industrial 55 cy7c136-55jc 51-85004 52-pin plastic leaded chip carrier commercial cy7c136-55jxc 52-pin plastic leaded chip carrier (pb-free) cy7c136-55nc 51-85042 52-pin plastic quad flatpack cy7c136-55nxc 52-pin plastic quad flatpack (pb-free) cy7c136a-55jxi 51-85004 52-pin plastic leaded chip carrier (pb-free) industrial cy7c136a-55nxi 51-85042 52-pin plastic quad flatpack (pb-free) 55 cy7c146-55jxc 51-85004 52-pin plastic leaded chip carrier (pb-free) commercial cy family: dual-port sram 7 c xxx technology: cmos company id: cy = cypress density temperature grade: commercial xx as x c pb-free (rohs compliant) package: j = plcc; n = pqfp speed grade: 25/55 ns [+] feedback
cy7c132, cy7c136 cy7c136a, cy7c142, cy7c146 document #: 38-06031 rev. *g page 14 of 15 package diagrams figure 17. 52-pin plastic leaded chip carrier, 51-85004 figure 18. 52-pin plastic quad flatpack, 51-85042 51-85004 *b 51-85042 *a [+] feedback
document #: 38-06031 rev. *g revised november 24, 2010 page 15 of 15 all products and company names mentioned in this docum ent may be the trademarks of their respective holders. cy7c132, cy7c136 cy7c136a, cy7c142, cy7c146 ? cypress semiconductor corporation, 2005-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreemen t with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reas onably be expected to result in significa nt injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or impl ied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress re serves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb document title: cy7c132, cy7c136, cy7c136a, cy7c142, cy7c146 2k x 8 dual-port static ram document number: 38-06031 revision ecn submission date orig. of change description of change ** 110171 10/21/01 szv change from spec number: 38-06031 *a 128959 09/03/03 jfu added cy7c136-55ni to order information *b 236748 see ecn ydt removed cross information from features section *c 393184 see ecn yim added pb-free logo added pb-free parts to ordering information: cy7c136-25jxc, cy7c136-25nxc, cy7c136-55jxc, cy7c136-55nxc, cy7c136-55jxi, cy7c136-55nxi, cy7c146-25jxc, cy7c146-55jxc *d 2623658 12/17/08 vkn/pyrs added CY7C136-25JXI part removed cy7c132/142 from the ordering information table removed 48-pin dip and 52-pin square lcc package from the data sheet *e 2678221 03/24/2009 vkn/aesa added cy7c136a-55jxi, and cy7c136a-55nxi parts. *f 2896210 03/22/2010 rame updated ordering information updated package diagrams *g 3094400 11/24/10 admu removed partnumber cy7c 136-55ji from the ordering information table. added ordering code definitions. [+] feedback

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